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74LS76 Dual JK Flip-Flop with Set and Clear IC – Hitachi (7476 IC) DIP-16 Package

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₹190.00 (excluding 18% GST)

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Description

The 74LS76 is a TTL logic IC featuring two independent JK flip-flops with asynchronous set and clear functions. This IC allows for data storage and timing operations in digital circuits, with the added capability of immediate resetting or setting of the flip-flops regardless of the clock signal.

Features

  • Dual JK flip-flops: Two separate JK flip-flops in one package.
  • Positive edge-triggered: Flip-flops change state on the rising edge of the clock signal.
  • Asynchronous set and clear: Each flip-flop has asynchronous set (S) and clear (R) inputs that override the clock and other inputs, allowing for immediate setting or clearing.
  • Complementary outputs: Provides both Q and Q̅ outputs for each flip-flop.
  • Standard TTL logic levels: Designed to interface with TTL logic families.

Specifications

  • Package Type: DIP-16 (Dual In-line Package)
  • Number of Flip-Flops: 2
  • Supply Voltage (Vcc): 4.75V to 5.25V
  • Propagation Delay Time: 15 ns (typical at 5V)
  • Setup Time: 20 ns (typical at 5V)
  • Hold Time: 5 ns (typical at 5V)
  • Output Drive Current: ±8 mA (source/sink)
  • Operating Temperature: 0°C to 70°C

Note

* Product Images are shown for illustrative purposes only and may differ from actual product

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