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74LS109 Dual J-K Positive Edge-Triggered Flip-Flop IC (74109 IC) DIP-16 Package

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25 In stock


Note: Any order placed will take 15 days for dispatch.

76.00 (excluding 18% GST)

25 In stock

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Description

The 74LS109 is a dual J-K positive edge-triggered flip-flop with clear and preset capabilities. It features two independent J-K flip-flops, each with set (preset) and reset (clear) inputs. The device operates on positive edge-triggering, meaning the output state changes on the rising edge of the clock input. It is part of the 74LS (Low Power Schottky) logic family, offering low power consumption and fast switching speeds. This IC is commonly used in counters, shift registers, and memory circuits.

Features

  • Logic Family: 74LS series (Low Power Schottky)
  • Logic Function: Dual J-K positive edge-triggered flip-flop
  • Positive edge-triggered clock input
  • Individual preset (set) and clear (reset) inputs for each flip-flop
  • Toggle capability with J and K inputs
  • TTL compatible inputs and outputs
  • Asynchronous reset and preset
  • Low power consumption
  • High noise immunity
  • Operating temperature: 0°C to +70°C

Specifications

  • Supply Voltage (Vcc): 4.75V to 5.25V
  • Input High Voltage (VIH): Minimum 2V
  • Input Low Voltage (VIL): Maximum 0.8V
  • Output High Voltage (VOH): Minimum 2.7V
  • Output Low Voltage (VOL): Maximum 0.5V
  • Maximum Propagation Delay: 25ns (typical)
  • Power Dissipation: 15mW (typical)
  • Fan-Out: 10 LS-TTL loads
  • Package: DIP-16 (Dual In-Line Package with 16 pins)

Note

* Product Images are shown for illustrative purposes only and may differ from actual product

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