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74HC109 Dual J-K Negative-Edge-Triggered Flip-Flops IC (74109) DIP-16 Package

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₹19.00 (excluding 18% GST)

25 In stock

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Description

The 74HC109 is a dual J-K flip-flop with negative-edge triggering. It features asynchronous set (SD) and reset (RD) inputs, allowing immediate changes in output independent of the clock signal. The device operates on the falling edge of the clock pulse and is designed for high-speed CMOS logic applications.

Features

  • Dual J-K flip-flops
  • Negative-edge clock triggering
  • Asynchronous set (SD) and reset (RD) inputs
  • TTL-compatible inputs and outputs
  • High-speed CMOS operation
  • Low power consumption
  • Standard DIP-16 package for easy through-hole integration

Specifications

  • Logic Family: 74HC (High-Speed CMOS)
  • Number of Flip-Flops: 2
  • Edge Triggering: Negative (falling edge)
  • Asynchronous Inputs: Set (SD) and Reset (RD)
  • Supply Voltage (Vcc): 2V to 6V
  • Input Low Voltage (VIL): Max 0.3Vcc
  • Input High Voltage (VIH): Min 0.7Vcc
  • Output Low Voltage (VOL): Max 0.1Vcc (at IOL = 4mA)
  • Output High Voltage (VOH): Min 0.9Vcc (at IOH = -4mA)
  • Power Dissipation: 1 µW (typical static)
  • Propagation Delay: 20 ns (at Vcc = 5V)
  • Operating Temperature Range: -40°C to 85°C
  • Package Type: DIP-16

Note

* Product Images are shown for illustrative purposes only and may differ from actual product

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