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74F113 Dual JK Negative Edge-Triggered Flip-Flop IC (74113) DIP-16 Package

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Description

The 74F113 is a dual J-K flip-flop IC featuring negative edge-triggered operation, which means it changes state on the falling edge of the clock signal. Each flip-flop within the IC has independent J, K, clock, preset (PR), and clear (CLR) inputs, providing flexibility in logic design. The 74F113 is commonly used in digital systems for applications like counters, registers, and other sequential logic circuits where fast and reliable performance is essential.

Features

  • Dual J-K Flip-Flops: Contains two independent flip-flops in a single package.
  • Negative Edge-Triggered: State transitions occur on the falling edge of the clock signal.
  • Individual Preset and Clear Inputs: Allows for asynchronous control, enabling immediate setting or resetting of the flip-flop states.
  • High-Speed Operation: Optimized for fast switching in digital circuits.
  • Versatile Functionality: Capable of toggle, set, reset, and hold operations.
  • Standard TTL Compatibility: Works seamlessly with TTL logic levels.
  • DIP-16 Package: Compact 16-pin Dual In-line Package for easy integration into circuits.

Specifications

  • Logic Family: 74F (Fast TTL)
  • Function: J-K Negative Edge-Triggered Flip-Flops
  • Number of Bits: 2 (Dual Flip-Flops)
  • Package Type: DIP-16
  • Propagation Delay (Max): 4.5 ns
  • Supply Voltage (Vcc): 4.75V to 5.25V
  • Operating Temperature Range: 0°C to +70°C
  • Output Current: 20mA (max per output)
  • Input Capacitance: 5pF (typical)
  • Power Dissipation: 19mW (typical per flip-flop)

Note

* Product Images are shown for illustrative purposes only and may differ from actual product

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