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74F109 Positive J-K Positive Edge-Triggered Flip-Flops IC (74109) DIP-16 Package

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Description

The 74F109 is a dual J-K flip-flop with individual set (S) and reset (R) inputs. The device is positive edge-triggered, meaning that it changes state on the rising edge of the clock signal. This IC is often used in applications requiring high-speed flip-flops for data storage, counters, and shift registers. The J and K inputs allow for toggle, set, reset, and hold functions, providing versatile control over the output states.

Features

  • Dual J-K Flip-Flops: Two independent J-K flip-flops in a single package.
  • Positive Edge-Triggered: State changes on the rising edge of the clock signal.
  • Individual Set and Reset Inputs: Allows for asynchronous control of the flip-flop states.
  • High-Speed Operation: Designed for high-speed digital logic circuits.
  • Toggle, Set, Reset, and Hold Functions: Versatile control over the output state.
  • Standard TTL Compatible: Operates with standard TTL logic levels.
  • DIP-16 Package: 16-pin Dual In-line Package for easy integration into standard PCBs

Specifications

  • Logic Family: 74F (Fast TTL)
  • Function: J-K Positive Edge-Triggered Flip-Flops
  • Number of Bits: 2 (Dual Flip-Flops)
  • Package Type: DIP-16
  • Propagation Delay (Max): 4.5 ns
  • Supply Voltage (Vcc): 4.75V to 5.25V
  • Operating Temperature Range: 0°C to +70°C
  • Output Current: 20mA (max per output)
  • Input Capacitance: 5pF (typical)
  • Power Dissipation: 19mW (typical per flip-flop)

Note

* Product Images are shown for illustrative purposes only and may differ from actual product

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